FIG. 12 is a circuit diagram showing a conventional semiconductor memory device (for instance Patent Document 1). In the semiconductor memory device 100, bit lines 104 and 106 are connected to a sense amplifier 102. To the bit lines 104 and 106, reference cells 110 and 120 are connected respectively. The reference cells 110 and 120 are connected to a common potential line 108. As described later, a reference potential is written to the reference cells 110 and 120 via this potential line 108.
The reference cell 110 is constituted by a capacitor 112 and transistors 114 and 116. Similarly, the reference cell 120 is constituted by a capacitor 122 and transistors 124 and 126 Word lines 152, 154, 156, and 158 are connected to gates of the transistors 124, 126, 114, and 116 respectively.
Memory cells 1301 to 130n are connected to the bit line 104. “n” is an integer equal to or greater than 2, for instance 128 or 256. Further, memory cells 1401 to 140n are connected to the bit line 106. Each of the memory cells 1301 to 130n is constituted by a capacitor 132 and a transistor 134. Word lines 1621 to 162n are respectively connected to gates of the transistors 134 of the memory cells 1301 to 130n. Similarly, each of the memory cells 1401 to 140n is constituted by a capacitor 142 and a transistor 144. Word lines 1641 to 164n are respectively connected to gates of the transistors 144 of the memory cells 1401 to 140n. 
The read operation of the semiconductor memory device 100 will be described with reference to a timing chart in FIG. 13. In FIG. 13, the potentials of the word lines 152, 154, 156, 158, 1621, and 1641 are denoted by lines L152, L154, L156, L158, L1621, and L1641 respectively. Here, a case where data is read from the memory cells 1301 and 1401 consecutively will be explained.
First, by activating the word line 152 thereby turning on the transistor 124, the reference potential is written to the reference cell 120 via the potential line 108. The reference potential could be, for instance, ½ Vcc (a half of a power supply voltage). Here, “writing the reference potential to the reference cell” means that one end of the capacitor within the reference ell is made conductive with the potential line by turning on the transistor connected to the potential line out of the transistors constituting the reference cell. Next, after the word line 152 is deactivated thereby turning off the transistor 124, the word lines 154 and 1621 are activated. Then the transistors 126 and 134 are turned on, the potentials of the memory cell 1301 and the reference cell 120 are compared by the sense amplifier 102, and as a result, data is read from the memory cell 1301.
Next, by activating the word line 156 thereby turning on the transistor 114, the reference potential is written to the reference cell 110 via the potential line 108. Then, after the word line 156 is deactivated thereby turning off the transistor 114, the word lines 158 and 1641 are activated As a result, the transistors 116 and 144 are turned on, and data is read from the memory cell 1401.
FIGS. 14A and 14B are graphs showing how the potentials of the bit lines 104 and 106, the reference cell 120, and the memory cell 1301 change during data read-out. FIGS. 14A and 14B correspond to cases where the potential read out from the memory cell 130, is HIGH and LOW respectively. In these graphs, the ordinate and abscissa represent potential V and time t, respectively. Lines L104, L106, L120, and L1301 respectively denote the potentials of the bit lines 104 and 106, the reference cell 120, and the memory cell 1301. Further, arrow A1 indicates a point in time when the sense amplifier 102 is activated and arrow A2 indicates a point in time when the equalization of the bit lines 104 and 106 starts.
As shown in FIG. 14A, in the case where the potential read out from the memory cell 1301 is HIGH, the potentials of the bit lines 104 and 106 get closer to the HIGH and LOW levels respectively when the sense amplifier 102 is activated. At the same time, the potential of the reference cell 120 gets closer to the LOW level. On the other hand, as shown in FIG. 14B, in the case where the potential read out from the memory cell 1301 is LOW, the potentials of the bit lines 104 and 106 get closer to the LOW and HIGH levels respectively when the sense amplifier 102 is activated. At the same time, the potential of the reference cell 120 gets closer to the HIGH level.
Other than Patent Document 1, prior art documents related to the present invention are as follows: Patent Document 2, Patent Document 3, and Patent Document 4.    [Patent Document 1]    Japanese Patent Kokai Publication No. JP-P2006-278778A    [Patent Document 2]    Japanese Patent Kokai Publication No. JP-A-6-12860    [Patent Document 3]    Japanese Patent Kokai Publication No. JP-P2005-228446A    [Patent Document 4]    Japanese Patent Kokai Publication No JP-P2001-68636A